Capacitors are used in integrated circuit designs to achieve different functions such as dynamic random access memories, bypassing, resonant circuits, filters, and mix-signal applications, for example. A conventional capacitor in an integrated circuit has two flat conductive plates, with one on the top of the other, and an intervening layer of dielectric material. Such capacitors having a sandwich structure are often referred to as metal-insulator-metal (MIM) capacitors. One disadvantage of this structure is the relatively large area of the chip that is required to obtain a desired capacitance.
One approach to reducing the required chip area involves stacking several layers of conductive plates, which are alternately connected to form opposite electrodes of the capacitor. Another approach to reducing the required chip area involves the use of a layer of parallel interdigitated strips as electrodes having a dielectric material therebetween. Such a structure provides a higher capacitance value per unit area, as a result of the increased electrode (plate) area afforded by the opposing top, bottom, and sidewall surfaces. Such capacitors having an interdigitated structure are often referred to as metal-oxide-metal (MOM) capacitors. For purposes of discussion herein, “MOM capacitors” is used generally to refer to capacitors having an interdigitated capacitor structure, regardless of layout and regardless of material choices for the electrodes and the dielectric material(s) therebetween.
FIG. 1 illustrates a prior art MOM capacitor 20 having parallel strips 22, 24, 26, 28 in the first layer 30, which are alternately connected to the first bus 32 and second bus 34. Strips 22 and 26 are connected to the first bus 32 with the same polarity. Strips 24 and 28 are connected to the second bus 34 with the opposite polarity to the first bus 32. At least one more layer of the same structure overlies the first layer 30. FIG. 2A shows the MOM capacitor structure 20 in cross section through the strips, along line 2-2 in FIG. 1. The first buses (e.g., 32) of different layers and the second buses (e.g., 34) of different layers are respectively connected by vias (not shown). Dielectric material (not shown) is filled between strips of the same and different layers.
Because the interdigitated fingers of each layer are parallel to each other in this structure 20 of FIG. 2A, any misalignment of strips from one layer to the next, caused, for example, by overall registration errors, will change relative positions between the electrodes. As a result, the overall capacitance of the structure will deviate from the expected value and affect the performance of the integrated circuit. FIG. 2B is a variation on FIG. 2A, which includes conductive vias 27 connecting between the fingers (FVMOM, Finger-Via MOM device). Thus, one disadvantage of prior art interdigitated capacitors is the undesired variance of capacitance caused by misalignment of strips between adjacent layers because capacitance varies when the relative position between parallel strips of two adjacent layers changes.
FIG. 3 shows another alternative MOM capacitor structure 36 in cross-section through the strips, along line 3-3 in FIG. 1. In comparing FIG. 3 to FIG. 2A, FIG. 3 provides another alternative for the placement of electrodes in one layer relative another layer. Each capacitor shown in FIGS. 1-3 may be laid out in an individual terminal routing as shown schematically in FIG. 4 (second matched capacitor not shown in FIGS. 1-3). FIG. 5 is a schematic showing another way that capacitors are sometimes connected, which is referred to a common terminal routing. In a typical common terminal routing configuration, two capacitors C1 and C2 share a common ground electrode 40.
MOM capacitors typically have many advantages over MIM capacitors and generally provide better performance across the board. For example, in comparison to a typical MIM capacitor, a MOM capacitor structure usually will have better capacitance per unit, better compatibility with the use of low-k dielectric materials and processes associated with the formation of low-k dielectric structures, ability to have a higher breakdown voltage, better temperature coefficient of change, ability for use in higher voltage applications (better VCC), and same or better Q-factor. However, mismatch of electrical characteristics is often more problematic in conventional MOM capacitors than in MIM capacitors, e.g., where a pair of capacitors are desired to be identical (electrically). It is preferable to minimize mismatch in MOM capacitors. For example, in an array of MOM capacitors for an analog-to-digital converter, it will be desirable to have the capacitors as closely matched as possible. Mismatch problems usually stem from layout design and process sensitivities. Process sensitivities may be caused by variations across a wafer. For example, uneven etching across a wafer or an uneven flow of gases at one point on a wafer compared to another may cause variations from one location to another on a same wafer or on a same chip. Feature density differences may also cause variations in etch rate, thereby creating a process sensitivity. In a damascene process, for example, more critical process sensitivity source comes from Cu CMP (e.g., Cu Pattern density, slurry uniformity, and deformation from polish pad).
FIG. 6 shows a pair of MOM capacitors C1 and C2 of the prior art having a common terminal routing configuration. The positive electrode 42 of capacitor C1 in FIG. 6 has a set of positive fingers 44 that are interdigitated with fingers 46 of the common ground electrode 40. Similarly, the positive electrode 48 of capacitor C2 in FIG. 6 has a set of positive fingers 50 that are interdigitated with fingers 46 of the common ground electrode 40, but at a different location. One of disadvantages of this configuration is that capacitors C1 and C2 in FIG. 6, each consumes its own footprint area, in spite of the shared common ground electrode 40. If capacitors C1 and C2 are intended to be matched to etch other, i.e., providing essentially identical capacitance characteristics, then another disadvantage of the configuration of FIG. 6 is the mismatch effects that may be caused by capacitor C1 being located at a location different than that of capacitor C2.
FIG. 7 shows a pair of cross-coupled capacitors C1 and C2 of the prior art having another common terminal routing configuration. In FIG. 7, part of capacitors C1 and C2 are on the right side and parts of capacitors C1 and C2 are on the left side of the structure 52. Also, part of capacitors C1 and C2 are on the upper side and parts of capacitors C1 and C2 are on the lower side of the structure 52. Thus, processing variations on the right side of the structure 52 are more likely to be experienced by both capacitors C1 and C2. Likewise, processing variations on the bottom side of the structure 52 are more likely to be experienced by both capacitors C1 and C2. This allows capacitors C1 and C2 to be more closely matched relative to each other, or at least less sensitive to process variations. The cross-coupling provided by the structure 52 of FIG. 7 has been shown to dramatically reduce mismatch effects, as compared to the structure 51 of FIG. 6. A disadvantage of the prior art structure 52 of FIG. 7 is the amount of footprint area required for the structure.
There is a constant drive in the semiconductor industry to reduce the amount of chip real estate used by devices for many reasons (e.g., providing higher operating speeds, providing more devices per wafer for greater processing yields). Hence, there is a need for MOM capacitor structures that reduce mismatch effects while also reducing the amount of chip real estate required to provide the devices.